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MC14521B 24-Stage Frequency Divider
The MC14521B consists of a chain of 24 flip-flops with an input circuit that allows three modes of operation. The input will function as a crystal oscillator, an RC oscillator, or as an input buffer for an external oscillator. Each flip-flop divides the frequency of the previous flip-flop by two, consequently this part will count up to 224 = 16,777,216. The count advances on the negative going edge of the clock. The outputs of the last seven-stages are available for added flexibility.
Features
http://onsemi.com MARKING DIAGRAMS
16 MC14521BCP AWLYYWWG 1
* All Stages are Resettable * Reset Disables the RC Oscillator for Low Standby Power Drain * RC and Crystal Oscillator Outputs Are Capable of Driving External * * * * *
Loads Test Mode to Reduce Test Time VDD and VSS Pins Brought Out on Crystal Oscillator Inverter to Allow the Connection of External Resistors for Low-Power Operation Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load over the Rated Temperature Range Pb-Free Packages are Available*
1
PDIP-16 P SUFFIX CASE 648
SOIC-16 D SUFFIX CASE 751B 1
16 14521BG AWLYWW 1
16 SOEIAJ-16 F SUFFIX CASE 966 1 1 MC14521B ALYWG
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Value -0.5 to +18.0 -0.5 to VDD +0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C
A WL, L YY, Y WW, W G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 6
Publication Order Number: MC14521B/D
MC14521B
BLOCK DIAGRAM
RESET 2
9 IN 1
6 IN 2 5 VDD 4 OUT2
STAGES 1 THRU 17 VDD = PIN 16 VSS = PIN 8
STAGES 18 THRU 24 Q18 Q19 Q20 Q21 Q22 Q23 Q24
PIN ASSIGNMENT
Q24 RESET VSS OUT 2 VDD IN 2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q23 Q22 Q21 Q20 Q19 Q18 IN 1 7 OUT 1
VSS
3
10
11
12
13
14
15
1
Output Q18 Q19 Q20 Q21 Q22 Q23 Q24
Count Capacity 218 = 262,144 219 = 524,288 220 = 1,048,576 221 = 2,097,152 222 = 4,194,304 223 = 8,388,608 224 = 16,777,216
ORDERING INFORMATION
Device MC14521BCP MC14521BCPG MC14521BD MC14521BDG MC14521BDR2 MC14521BDR2G MC14521BF MC14521BFG MC14521BFEL MC14521BFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) 2000 / Tape & Reel 50 Units / Rail 2500 / Tape & Reel 48 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC14521B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
- 55_C VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH 5.0 5.0 10 15 5.0 5.0 10 15 IOL 5.0 10 15 15 - 5.0 10 15 5.0 10 15 - 1.2 - 0.25 - 0.62 - 1.8 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 - - - - - - - - - - - - - - - - 0.1 - 5.0 10 20 - 1.0 - 0.2 - 0.5 - 1.5 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 - - - - - - 1.7 - 0.36 - 0.9 - 3.5 - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 - - - - - - - - - - - 0.1 7.5 5.0 10 20 - 0.7 - 0.14 - 0.35 - 1.1 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 - - - - - - - - - - - - - - - - 1.0 - 150 300 600 mAdc 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - mAdc 25_C 125_C Characteristic Symbol VOL Min - - - 4.95 9.95 14.95 - - - Max Min - - - 4.95 9.95 14.95 - - - Typ (Note 2) 0 0 0 5.0 10 15 2.25 4.50 6.75 Max Min - - - 4.95 9.95 14.95 - - - Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 - - - 1.5 3.0 4.0 0.05 0.05 0.05 - - - 1.5 3.0 4.0 0.05 0.05 0.05 - - - 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD VOH Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) Pins 4 & 7 (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) Pins 1, 10, (VOH = 9.5 Vdc) 11, 12, 13, 14 (VOH = 13.5 Vdc) and 15 (VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (Note 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL Vdc mAdc Iin Cin IDD mAdc pF mAdc IT IT = (0.42 mA/kHz) f + IDD IT = (0.85 mA/kHz) f + IDD IT = (1.40 mA/kHz) f + IDD mAdc 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003.
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MC14521B
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SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Vdc 5.0 10 15 Min - - - Typ (Note 6) 100 50 40 Max 200 100 80 Unit ns Output Rise and Fall Time (Counter Outputs) tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns Propagation Delay Time Clock to Q18 tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns Clock to Q24 tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns Propagation Delay Time Reset to Qn tPHL = (1.7 ns/pF) CL + 1215 ns tPHL = (0.66 ns/pF) CL + 467 ns tPHL = (0.5 ns/pF) CL + 350 ns Clock Pulse Width tTLH, tTHL tPHL, tPLH 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 tWH(cl) 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 - - - 385 150 120 - - - - - - 1400 600 450 30 0 - 40 1300 500 375 140 55 40 3.5 9.0 12 - - - 700 300 225 - 200 - 160 - 110 2600 1000 750 - - - 2.0 5.0 6.5 15 5.0 4.0 - - - - - - ns - - - - - - 4.5 1.7 1.3 6.0 2.2 1.7 9.0 3.5 2.7 12 4.5 3.5 ns ms Clock Pulse Frequency fcl MHz Clock Rise and Fall Time tTLH, tTHL ms Reset Pulse Width tWH(R) ns Reset Removal Time trem ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 500 mF VDD PULSE GENERATOR IN 2 ID VDD Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS CL CL CL CL CL Vin 20 ns 90% 10% 50% 20 ns VDD 0V 0.01 mF CERAMIC 50% DUTY CYCLE R VSS CL CL
Figure 1. Power Dissipation Test Circuit and Waveform
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MC14521B
VDD VDD PULSE GENERATOR IN 2 VDD Q18 Q19 Q20 Q21 Q22 Q23 Q24 VSS IN 2 CL CL 20 ns 10% tWL Qn 50% 90% 10% tPLH tTLH tPHL tTHL 50% 20 ns 90% tWH 20 ns
CL CL CL
R VSS
CL CL
Figure 2. Switching Time Test Circuit and Waveforms
Characteristic Crystal Characteristics Resonant Frequency Equivalent Resistance, RS VDD Ro 18 M VDD R* VDD External Resistor/Capacitor Values Ro CT CS Frequency Stability Frequency Change as a Function of VDD (TA = 25_C) VDD Change from 5.0 V to 10 V VDD Change from 10 V to 15 V Frequency Change as a Function of Temperature (VDD = 10 V) TA Change from - 55_C to + 25_C MC14521 only Complete Oscillator* TA Change from + 25_C to + 125_C MC14521 only Complete Oscillator*
500 kHz Circuit 500 1.0 47 82 20
50 kHz Circuit 50 6.2 750 82 20
Unit kHz kW kW pF pF
CS
CT
IN 1 OUT 1 OUT 2 Q18 Q19 IN 2 Q20 Q21 Q22 Q23 R Q24 VSS VSS R*
+ 6.0 + 2.0 - 4.0 + 100
+ 2.0 + 2.0 - 2.0 + 120
ppm ppm ppm ppm
- 2.0 - 160
- 2.0 - 560
ppm ppm
Figure 3. Crystal Oscillator Circuit
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Figure 4. Typical Data for Crystal Oscillator Circuit http://onsemi.com
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*Optional for low power operation, 10 kW R 70 kW.
*Complete oscillator includes crystal, capacitors, and resistors.
MC14521B
8.0 FREQUENCY DEVIATION (%) 4.0 0 -4.0 -8.0 -12 -16 -55
RTC = 56 kW, C = 1000 pF
100 VDD = 15 V TEST CIRCUIT FIGURE 7 f, OSCILLATOR FREQUENCY (kHz) 50 20 10 5.0 2.0 1.0 0.5 0.2 f AS A FUNCTION OF C (RTC = 56 kW) (RS = 120 k)
VDD = 10 V
TEST CIRCUIT FIGURE 7 f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC)
10 V
5.0 V
{
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25C
0.1 125
-25 0 25 50 75 100 TA, AMBIENT TEMPERATURE (C), DEVICE ONLY
1.0 k
0.0001
10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (mF)
1.0 m 0.1
Figure 5. RC Oscillator Stability
RS C VDD VDD RTC VDD
Figure 6. RC Oscillator Frequency as a Function of RTC and C
VDD VDD Q18 Q19 Q20 Q21 IN 2 Q22 Q23 Q24 OUT 1 R OUT 2 VSS VSS IN 1
IN 1 OUT 1 OUT 2 Q18 Q19 IN 2 Q20 Q21 Q22 Q23 R Q24 VSS VSS
PULSE GENERATOR
Figure 7. RC Oscillator Circuit
Figure 8. Functional Test Circuit
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FUNCTIONAL TEST SEQUENCE
Inputs Outputs Comments Reset In 2 Out 2 VSS VDD Q18 thru Q24 0 First "0" to "1" transition on In 2, Out 2 node. 255 "0" to "1" transitions are clocked into this In 2, Out 2 node. Counter is in three 8-stage sections in parallel mode Counter is reset. In 2 and Out 2 are connected together. 1 0 A test function (see Figure 8) has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections, and 255 counts are loaded in each of the 8-stage sections in parallel. All flip-flops are now at a logic "1". The counter is now returned to the normal 24-stages in series configuration. One more pulse is entered into Input 2 (In 2) which will cause the counter to ripple from an all "1" state to an all "0" state. 0 1 0 1 - - - 1 0 0 1 1 0 0 1 0 1 - - - 1 0 0 0 0 1 GND VDD 1 1 1 1 1 0 Counter converted back to 24-stages in series mode. Out 2 converts back to an output. Counter ripples from an all "1" state to an all "0" stage. VDD GND The 255th "0" to "1" transition.
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MC14521B
LOGIC DIAGRAM
VDD 5 RESET 2
9 IN 1
1
2
STAGES 3 THRU 7
8
6 IN 2 7 OUT 1 3 VSS
4 OUT 2
9
10
STAGES 11 THRU 15
16
17
18
19
20
21
22
23
24
10 Q18
11 Q19
12 Q20
13 Q21
14 Q22
15 Q23
1 Q24
VDD = PIN 16 VSS = PIN 8
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MC14521B
PACKAGE DIMENSIONS
PDIP-16 CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14521B
PACKAGE DIMENSIONS
SOEIAJ-16 CASE 966-01 ISSUE A
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC14521B/D

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